VMEM Simulator
Virtual Memory & Page Table Simulator | Step-by-step address translation with TLB and page replacement
Configuration
Virtual Addr Bits
12
16
20
Physical Addr Bits
10
12
16
Page Size
256B
512B
1KB
4KB
TLB Entries
0 (Off)
4
8
16
Replacement Algorithm
FIFO
LRU
Clock
Optimal (Belady)
Apply Config
Reset All
Address Input
Virtual Address (hex)
Read
Write
Access Address
Sequence Controls
|<
Step
Run
Pause
Reset
Speed
500ms
Presets
Sequential Scan
Random Access
Working Set
Stack + Heap
Thrashing
Belady's Anomaly
Statistics
Total Accesses
0
Page Faults
0
Fault Rate
0%
TLB Hits
0
TLB Hit Rate
0%
Evictions
0
Dirty Writebacks
0
TLB
Access Log
Event Log